Circuit Design Engineer – Active Security Clearance

SGS_JOB_2578

Engineering
 Massachusetts
Cadence IC design flow (layout
DRC
LVS
parasitic extraction)
Calibre
Assura
CMOS layout (12nm–65nm)
Floor planning
Block-level design
Tape outs
Mixed-signal/Analog layout
Top-level verification

Contract - 1+ years

Location (mandatory): Lexington, MA 02421, United States (Remote The client develops custom digital & mixed-signal Readout Integrated Circuits (ROICs) for advanced imager applications. They are seeking an analog/mixed-signal layout design engineer to support the implementation of imager circuit building blocks. This position is remote with occasional travel (up to 3+ trips per year) to Lexington, MA. An active security clearance is required.

Job Responsibilities:

  • Design and develop circuits used in electronic devices.
  • Perform layout and mask design, device evaluation, and characterization.
  • Design test boxes, construct prototypes, and determine wafer fabrication processes.
  • Prepare test methods and specifications.
  • Analyze equipment to establish operating data and conduct experimental tests.
  • Provide finished device approval and prepare customer application information.
  • Physical layout and verification of integrated circuit building blocks.
  • Full-chip assembly and top-level verification.
  • Apply best practices for managing local process variation through layout techniques.
  • Utilize high-speed digital and RF layout techniques to minimize parasitic interactions.

Skills:

  • Deep-submicron CMOS layout experience (12–65 nm, multiple foundries including Global Foundries, On Semi, and Tower Jazz).
  • Proficiency with Cadence IC design flow including layout, DRC, LVS, and parasitic extraction (Calibre and Assura).
  • Extensive experience in top-level floor planning and block-level design.
  • Proven record of multiple design tape outs.
  • Strong interpersonal, verbal, and written communication skills to support collaboration in multi-person design teams.

Education/Experience:

  • Must currently hold an Active Secret Clearance or higher.
  • 10+ years of experience in Cadence IC design flow, CMOS layout (12nm–22nm), and floorplanning/block-level design.
  • Strong communication skills (team collaboration, verbal, and written).

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